1. Field of the Invention
The present invention relates to a signal duty detecting apparatus capable of detecting a duty of a signal, specifically, a duty of a pulse width modulation (PWM) signal and a motor driving apparatus having the same.
2. Description of the Related Art
A brushless direct current (BLDC) motor generally means a DC motor able to conduct current or having a function able to adjust a current direction using a non-contact position detector and a semiconductor element, rather than using a mechanical contact such as a brush, a commutator, or the like, in a DC motor.
In order to drive a BLDC motor, a driving apparatus may be used.
FIG. 1 shows a configuration of a general motor driving apparatus.
Referring to FIG. 1, a general motor driving apparatus 10 may include a controlling unit 11 and a driving unit 12.
The controlling unit 11 may control driving of the motor, and the driving unit 12 may drive the motor by turning four field effect transistors (FETs) on or off, according to a driving signal of the controlling unit 11.
FIG. 2 shows driving signals of the motor driving apparatus.
Referring to FIG. 2, the driving signals transferred from the controlling unit 11 to the driving unit 12 may be divided into four types of driving signals and transferred in a sequence of identification numbers {circle around (1)}, {circle around (2)}, {circle around (3)}, and {circle around (4)}.
That is, a first PMOS FET P1 and a second NMOS FET N2 may be turned on by a driving signal {circle around (1)}, and the first PMOS FET P1 and the second NMOS FET N2 may be turned off while a second PMOS FET P2 and a first NMOS FET N1 may be turned on by a driving signal {circle around (2)}.
Again, the second PMOS FET P2 and the first NMOS FET N1 may be turned off while the first PMOS FET P1 and the second NMOS FET N2 may be turned on by a driving signal {circle around (3)}, and the first PMOS FET P1 and the second NMOS FET N2 may be turned off while the second PMOS FET P2 and the first NMOS FET N1 may be turned on by a driving signal {circle around (4)}.
In this driving scheme, when the first PMOS FET P1 and the second PMOS FET P2 are turned on, pulse width modulation (PWM) signals (depicted as oblique line portions in FIG. 2) are generated, whereby a speed of the motor may be controlled.
FIG. 3 is an on-duty graph of a general PWM signal.
Referring to FIG. 3, the on-duty graph of a general PWM signal may have a rectangular shape.
As described above, the PWM signal may be used to drive the motor and the speed of the motor may be controlled according to an on-duty of the PWM signal. Therefore, as disclosed in the Related Art Document, a duty of the PWM signal is detected in order to precisely control the speed of the motor. Generally, in order to detect the duty of the PWM signal, a rising edge or a falling edge of the PWM signal is detected. To this end, a clock signal having a predetermined frequency is used.
However, in the case of a scheme of detecting the rising edge or the falling edge of the PWM signal using the clock signal, it may be difficult to detect an on-duty of 0% or an on-duty of 100% of the PWM signal, and an error may be generated due to the frequency of the clock signal.